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1 memory all data sheets are subject to change without notice (858) 503-3300- fax: (858) 503-3301 - www.maxwell.com 16-bit latchup protected 7809lp ?2001 maxwell technologies all rights reserved. analog to digital converter 12.19.01 rev 3 1000585 f eatures : ?r ad -p ak ? radiation-hardened against natural space radia- tion ? total dose hardness: - > 100 krad (si), depending upon space mission ? latch-up protection technology (lpt tm ) ? sel converted into a reset - rate based on cross section and mission ? same footprint as ads7809 ? package: 24 pin r ad -p ak flat package ? 100 khz min sampling rate ? 10 v and 0 v to 5 v input range ? advanced cmos technology ? dnl: 15-bits ?no missing codes? ? 83 db min sinad with 20 khz input ? single +5 v supply operation ? utilizes internal or external reference ? serial output ? power dissipation: 132 mw max d escription : maxwell technologies? 7809lp high-speed 16-bit analog to digital converter features a greater than 100 kilorad (si) total dose tolerance depending upon space mission. using max- well?s radiation-hardened r ad -p ak ? packaging technology, the 7809lp has the same footprint as ads7809 and is latchup protected by maxwell technologies? latchup protection tech- nology (lpt tm ). it is a 24 pin, 16-bit sampling analog-to-digital converter using state-of-the- art cmos structures. the 7809lp contains a 16-bit capacitor based sar a/d with s/h, reference, clock, interface fo r microprocessor use, and serial output drivers. the 7809lp is specified at a 100khz sampling rate, and guaranteed over the full temperature range. laser- trimmed scaling resistors provi de various input ranges include 10 v and 0 to 5 v, while the innovative design allows opera- tion from a single +5 v supply, with power dissipation of under 132 mw. maxwell technologies' patented r ad -p ak packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose toleranc e. this product is available with screening up to class k. buffer comparator serial data out successive approximation register and control logic clock internal +2.5v ref. 20 k ? 4 k ? data clock serial data 20 k ? 10 k ? 5 k ? cdac busy ref cap r1 in r2 in r3 in r/c cs power down logic diagram
memory 2 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 t able 1. 7809lp p in d escription p in s ymbol d escription 1 r1in analog input. 2 agnd1 analog ground. used internally as ground reference point. 3 r2in analog input. 4 r3in analog input. 5 cap reference buffer capacitor. 2.2 f tantalum to ground. 6 ref reference input/output. 2.2 f tantalum capacitor to ground. 7 agnd2 analog ground. 8 sb/btc select straight binary or binary two?s complement data output format. if high, data will be output in a straight binary format. if low, dat a will be output in a binary two?s complement format. 9 ext/int select external or inter nal clock for transmitting data. if hi gh, data will be output synchronized to the clock input on dataclk. if low, a conver t command will initiate the transmission of the data from the previous conversion, along with 16 clock pulses output on dataclk. 10 dgnd digital ground. 11 lpbit built in test function of the latchup protection. drive low during normal operation. 12 lpstatus latchup protection status output. lpst atus when high indicates latchup protection is active and output data is invalid. 13 vana analog supply input. nominally 5v. 14 vdig digital supply input. nominally 5v. 15 sync sync output. if ext/int is high, either a rising edge on r/c with cs low or a falling edge on cs with r/c high will output a pulse on sync sy nchronized to the external dataclk. 16 dataclk either an input or an output depending on the ext/int level. output data will be synchronized to this clock. if ext/int is low, dataclk wi ll transmit 16 pulses after each conversion, and then remain low between conversions. 17 data serial data output. data will be synchroniz ed to dataclk, with the format determined by the level of sb/btc . in the external clock mode, after 16-bits of data, the 7809lopo will output the level input of tag as long as cs is low and r/c is high. if ext/int is low, data will be valid on both the rising and falling edges of dataclk, and between conversions data will stay at the level of the tag input when the conversion was started. 18 tag tag input for use in external clock mode. if ext/int is high, the digital data input on tag will be output on data with a delay of 16 dataclk pulses as long as c s is low and r/c is high. 19 r/c read/convert input. with cs low, a falling edge on r/c puts the internal sample/hold into the hold state and starts a conversion. when ext/int is low, this also initiates the transmission of the data results from the previous conv ersion. if ext/int is high, a rising edge on r/c with c s low, or a falling edge on cs with r/c high, transmits a pulse on sync and initiates the transmission of data from the previous conversion. 20 cs chip select. internally or?ed with r/c .
memory 3 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 21 busy busy output. falls when a conv ersion is started, and remains low until the conversion is com- pleted and the data is latched into the output shift register. cs or r/c must be high when busy rises, or another conversion will start without time for signal acquisition. 22 pwrd power down input. if high, conversions are inhibited and power consum ption is significantly reduced. results from the previ ous conversions are maintained in the output shift register. 23 lpvana latchup protection analog supply. 24 lpvdig latchup protection digital supply. t able 2. 7809lp a bsolute m aximum r atings p arameter s ymbol m in m ax u nit analog inputs r1 in r2 in r3 in cap ref 1 1. indefinite short to agnd2, momentarily short to v ana . -25 -25 -25 v ana + 0.3 25 25 25 agnd2 - 0.3 v v v v ground voltage differences: dgnd, agnd2 -0.3 0.3 v v ana -- 7 v v dig 7v v dig to v ana -- 0.3 v specified performance -40 85 c digital inputs -0.3 v dig + 0.3 v storage temperature t stg -65 150 c t able 3. 7809lp dc a ccuracy s pecifications (s pecified p erformance -40 to +85c) p arameter m in t yp m ax u nit integral linearity error -40 to 85c -- -- -- -- 3 5 lsb 1 differential linearity error -40 to 85c -- -- -- -- -2, 3 -1, 6 lsb lsb no missing codes 2 15 -- -- bits transition noise 3 -- 1.3 -- lsb full scale error 4,5 -- -- 0.6 % full scale error 4,5 (using ext. 2.5000 v ref )--0.6% full scale error drift -- 7 -- ppm/ c t able 1. 7809lp p in d escription p in s ymbol d escription
memory 4 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 full scale error drift (using ext. 2.5000 v ref ) -- 2 -- ppm/ c bipolar zero error 4 -- -- 10 mv bipolar zero error drift -- 2 -- ppm/ c unipolar zero error 4 -40 to 85c -- -- -- -- 3 16 mv mv unipolar zero error drift -- 2 -- ppm/ c recovery to rated accuracy after power down (1 uf capacitor to cap) -- 1 -- ms power supply sensitivity (v dig = v ana = v d ) 4.75 v > v d < 5.2 v -40 to 85c -- -- -- -- 8 32 lsb lsb 1. lsb stands for least significant bit. one lsb is equal to 305 v. 2. not tested. 3. typical rms noise at worst case transitions and temperatures. 4. measured with various fixed resistors. 5. for bipolar input ranges, full scale error is the worst case of -full scale or +full scale untrimmed deviation from ideal fir st and last scale code transitions, di vided by the transition voltage ( not divided by the full-scale range) and includes the effect of offset error. for unipolar input ranges, full scal e error is the deviation of the last c ode transition divided by the transition volta ge. it also includes the effect of offset error. t able 4. 7809lp d igital i nputs (s pecified p erformance -40 to +85c) p arameter m in t yp m ax u nit v il v ih i il , i ih -0.3 2.0 -- -- -- -- 0.8 v d + 0.3 10 v v a t able 5. 7809lp a nalog i nput and t hroughput s peed (s pecified p erformance -40 to +85c) p arameter m in t yp m ax u nit voltage ranges 10 v, 0 v to 5 v see table 2. impedance capacitance -- 35 -- pf conversion time -- 7.6 8 s complete cycle (acquire and convert) -- -- 10 s throughput rate 1 1. tested by application of signal. 100 -- -- khz t able 3. 7809lp dc a ccuracy s pecifications (s pecified p erformance -40 to +85c) p arameter m in t yp m ax u nit
memory 5 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 t able 6. 7809lp ac a ccuracy s pecifications (s pecified p erformance -40 to +85c) p arameter m in t yp m ax u nit spurious-free dynamic range, f in = 20 khz 1 1. guaranteed by design. 90 100 -- db 2 2. all specifications in db are re ferred to a full-scale 10 v input. total harmonic distortion, f in = 20 khz 1 -- -100 -90 db signal-to-noise (noise + distortion) 1 f in = 20 khz -60 db input 83 -- 88 30 -- -- db signal-to-noise 1 , f in = 20 khz 83 88 -- db full-power bandwidth 1,3 3. full-power bandwidth defined as full-scale input frequency at which signal-to-noise (noise + distortion) degrades to 60 db. -- 250 -- khz t able 7. 7809lp s ampling d ynamics (s pecified p erformance -40 to +85c) p arameter m in t yp m ax u nit aperture delay -- 40 -- ns aperture jitter sufficient to meet ac specification transient response fs step -- 2 -- us overvoltage recovery 1 1. recovers to specified performance after 2 x fs input overvoltage. -- 150 -- ns t able 8. 7809lp r eference (s pecified p erformance -40 to +85c) p arameter c onditions m in t yp m ax u nit internal reference voltage no load 2.48 2.5 2.52 v internal reference source current (must be ext. buffer) -- 1 -- a external reference voltage range for speci- fied linearity 1 1. tested by application of signal. 2.3 2.5 2.7 v external reference current drain ext. 2.5000v ref -- -- 100 a
memory 6 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 t able 9. 7809lp d igital o utputs (s pecified p erformance -40 to +85c) p arameter c onditions m in t yp m ax u nit data format data coding pipeline delay serial 16-bits binary two?s complement or straight binary conversion results only availabl e after completed conversion data clock internal (output only when transmitting data) external (can run continually) selectable for internal or external data clock ext/int low ext/int high -- 0.1 2.3 -- -- 10 mhz v ol v oh i sink = 1.6 ma i source = 500 a -- 4 -- -- 0.4 -- v leakage current 1 1. not tested. high-z state, v out = 0v to v dig -- -- 10 a output capacitance 1 high-z state -- 15 -- pf t able 10. 7809lp p ower s upplies (s pecified p erformance -40 to +85c) p arameter c onditions m in t yp m ax u nit v dig must be < v ana 4.75 5 5.25 v v ana 4.75 5 5.25 v i dig -- 0.3 -- ma i ana -- 16 -- ma power dissipation pwrd low pwrd high v ana = v dig = 5v f s = 100 khz -- -- -- -- 132 350 mw
memory 7 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 t able 11. 7809lp c ontrol l ine f unctions for r ead and c onvert s pecific f unction cs r/c busy ext/int datacl k pwrd sb/btc o peration initiate conver- sion and output data using inter- nal clock 1 > 0 0 0 1 > 0 1 1 0 0 output output 0 0 x x initiates conversion ?n?. data from conversion ?n- 1? clocked out on data synchronized to 16 clock pulses output on data- clk initiates conversion ?n?. data from conversion ?n- 1? clocked out on data synchronized to 16 clock pulses output on data- clk initiate conver- sion and output data using exter- nal clock 1 > 0 0 1 > 0 1 > 0 0 0 1 > 0 1 1 0 > 1 1 1 1 0 0 1 1 1 1 1 input input input input input 0 0 x 0 0 x x x x x initiates conversion ?n? initiates conversion ?n? outputs a pulse on sync followed by data from con- version ?n? clocked out synchronized to external dataclk. outputs a pules on sync followed by data from con- version ?n-1? clocked out synchronized to external dataclk 1 . conversion ?n? in process. outputs a pulse on sync followed by data from con- version ?n-1? clocked out synchronized to external dataclk 1 . conversion ?n? in process. incorrect conver- sions 000 > 1xx0xcs or r/c must be high or a new conversion will be initiated without time for acquisition power down x x x x x x x x x x 0 1 x x analog circuitry powered. conversion will be initi- ated without time for acquisition analog circuitry disabled. data from previous con- version maintained in out- put registers
memory 8 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 selecting output format x x x x x x x x x x x x 0 3 1 serial data is output in binary two?s comple- ment format. serial data is output in straight binary format. 1. see figure 4 for constraints on pr evious data valid during conversion. t able 12. 7809lp i nput r ange c onnection a nalog i nput r ange c onnect r1 in via 200 ? to c onnect r2 in via 100 ? to c onnect r3 in to i mpedance 10v v in agnd cap 22.9 k ? 5v agnd v in cap 13.3 k ? 3.3v v in v in cap 10.7 k ? 0v to 10v agnd v in agnd 13.3k ? 0v to 5v agnd agnd v in 10.0 k ? 0v to 4v v in agnd v in 10.7 k ? t able 13. 7809lp c onversion and d ata t iming (t a = -40 c to 85 c unless otherwise specified ) s ymbol d escription m in t yp m ax u nit t1 convert pulse width 40 -- 6000 ns t2 busy delay -- -- 65 ns t3 busy low -- -- 8 s t4 busy delay after end of conversion -- 220 -- ns t5 aperture delay -- 40 -- ns t6 conversion time -- 7.6 8 s t7 acquisition time -- -- 2 s t6 + t7 throughput time -- 9 10 s t8 r/c low to dataclk delay -- 450 -- ns t9 dataclk period -- 440 -- ns t10 data valid to dataclk high delay 20 75 -- ns t11 data valid after dataclk low delay 100 125 -- ns t12 external dataclk 100 -- -- ns t13 external dataclk high 20 -- -- ns t able 11. 7809lp c ontrol l ine f unctions for r ead and c onvert s pecific f unction cs r/c busy ext/int datacl k pwrd sb/btc o peration
memory 9 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 t14 external dataclk low 30 -- -- ns t15 dataclk high setup time 20 -- t12 + 5 ns t16 r/c to cs setup time 10 -- -- ns t17 sync delay after dataclk high 15 -- 35 ns t18 data valid delay 25 -- 55 ns t19 cs to rising edge delay 25 -- -- ns t20 data available after cs low 6 -- -- s t able 14. 7809lp c onversion d ata t iming d escription a nalog i nput d igital o utput b inary t wo ? s c omplement (sb/btc low) s traight b inary (sb/btc h igh ) b inary c ode h ex c ode b inary c ode h ex c ode full scale range 10 5 3.33v 0v to 10v 0v to 5v 0v to 4v least signifi- cant bit (lsb) 305 v 153 v 102 v 153 v 76 v 61 v + full scale (fs - 1 lsb) 9.99969 5v 4.99984 7v 3.33323 1v 9.99984 7v 4.99992 4v 3.99993 8v 0111 1111 1111 1111 7fff 1111 1111 1111 1111 ffff midscale 0v 0v 0v 5v 2.5v 2v 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 one lsb below mid- scale -305 v -153 v -102 v 4.99984 7v 2.49992 4v 1.99993 9v 1111 1111 1111 1111 ffff 0111 1111 1111 1111 7fff -full scale -10v -5v 3.33333 3v 0v 0v 0v 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 t able 13. 7809lp c onversion and d ata t iming (t a = -40 c to 85 c unless otherwise specified ) s ymbol d escription m in t yp m ax u nit
memory 10 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 1. c onversion t iming f igure 2. s erial d ata t iming u sing i nternal c lock (cs , ext/int and tag tied low) f igure 3. c onversion and r ead t iming with e xternal c lock (ext/int tied high). r ead a fter c onversion
memory 11 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 4. c onversion and r ead t iming with e xternal c lock (ext/int tied high). r ead d uring c onversion
memory 12 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 5. o ffset /g ain c ircuits for u nipolar i nput r anges
memory 13 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 6. o ffset /g ain c ircuits for b ipolar i nput r anges lpt tm operation
memory 14 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 latchup protection technology (lpt tm ) automatically detects an increase in the supply current of the 7809lp con- verter due to a single event effect an d internally cycles the powe r to the converter off, th en on, which restores the steady state operation of the device. a simplified block diag ram of the 7809lp circuitry is shown in figure 7. the lpt tm circuitry consists of two power swit ch and current sensor blocks, an lpt tm controller block, a bit current load block, and an active input protection block. figure 7. 7809lp simplified block diagram the power switch/current sensor blocks sense the supply current drawn by the protected device on the analog and digital supply pins. when a threshold level is exceeded on ei ther supply line, indicating single event induced latchup of the protected device, a signal is sent to the lpt tm controller block. the lpt tm controller then drives the power switches to an off state which removes the power supplies from the protected device. at the same time, a signal is sent to open the active input protection circuits and the lpstatus output pin is activated. after a period of time suffi- cient to clear the latchup, the lpt tm controller drives the power switches and input protection back to the on state restoring the operation of the protected device. the bit circui t is used during system test to electrically trigger the latchup function by drawing current th rough the power switch/current sensor blocks sufficient to trigger the lpt tm pro- tection.
memory 15 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 differences between the 7809lp and the ads7809 because the 7809lp uses the ads7809 die to perform the anal og to digital conversion function, its operation and per- formance is very similar to the ads7 809 packaged part from burr-brown. in ge neral the operation and application will be the same for both parts. there are three primary differences: the operation of the supply pins, the operation of the additional lpbit and lpstatus pins, and the operation of the i/o pins when a latchup is detected. the ads7809 provides separate analog and digital supply pins, vana and vdig. these same supply pins on the 7809lprp should be connected to the analog and digital supplies. there is no limit to the capacitance that can be connected to these pins in the system application. the 7809lp package also provides access to the ads7809 die supply pins with the lpvana and lpvdig pins. the signal paths between the supply input pins and the respective die supply pins are low resistance during normal device operation. when an excessive supply current due to a single event latchup is sensed on either of the supply pins, the lpt tm circuit opens both paths to the die supply pins allowing the latchup condition to clear. the lpvana and lpv- dig pins allow access to the current sense circuitry for electrical testing at the component level and provide optimal locations for attaching supp ly decoupling capacitors. caution: the lpvana and lpvdig pins must not be con- nected to the respective power supplies since this will defeat the lpt tm power switch and could result in permanent latchup of the device during operation in a radiation envi ronment. electrolytic capacitors should not be connected to these decoupling pins because the large capacitance will increase the recovery time of the 7809lp. low esr ceramic capacitors should be used with a maximum of .2f per pin. the lpbit input provides a means to electrically test the lpt tm circuit. a high level on the this pin causes a preset current to be drawn in addition to the normal device current through the analog and digital current sensors. if the high level is maintained for a sufficient duration, it will trigger the lpt tm circuit which will cycle the power to the protected device. if the lpbit remains high, the lpt tm circuit will continuously cycle the supply voltages off then on. driving this input with a 10 s high level pulse is sufficient duration to assure the lpt tm circuit cycles the power off then on one time only. a high level on the lpstatus output indicates that the lpt tm circuit has removed power from the protected device. the lpstatus returns low when the powe r is restored. lpstatus can be used to generate an input to the system data processor indicating that an lpt tm cycle has occurred and the protected de vice output accuracy may not be met until after the respective re covery time to the event. during the time that power is removed from the protected device , it is critical that external circuitry driving the device i/ o pins does not back-drive the device supply through input protection diodes or similar integrated structures. back- driving of the supply through the device i/o pins could cont ribute to an extended or even a permanent latchup condi- tion. for the ads7809 testing has shown that for the normal signal range of operation on the analog input pins r1in, r2in, and r3in, latchup will not be sustained. in order to prevent back-driving the supply from the digital i/o pins data, sync, tag, r/c, cs , and pwrd, the 7809lp incorporates active input protection circuits. these ci rcuits act as transmission gate s in series with the digital inputs. during normal operation, these gates are on an d present low resistance connections between the package input pins and the respective die pins. when the lpt tm circuit detects a latchup, these gates are switched off and present a high resistance path between the package inputs and the die inputs. the protected i/o pins are crow barred during the latchup. the bidirectional signal, dataclk, is also protected by a transmission gate. dedicated digital outputs are not similarly protected since in most applications there will be no appreciable drive signal on these outputs to back-drive the pins. pull up resistors on these outputs should be 10 k ? or greater to limit the
memory 16 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 back-drive current. low on resistance, transmission gate circuits are also connected between the package pins and the die ref and cap pins. these gates minimize the transient loading on the external filter capacitors required on these pins. this greatly reduces the single event recove ry time of the 7809lp to full accuracy after an lpt tm cycle. during an lpt tm cycle, all outputs of the 7809lp ar e invalid and unpredictable until a fter the functional recovery time. after the functional recovery time, data conversions occu r with a degraded accuracy un til the full accuracy recovery time. a summary of the pin differences between the ads7809 and the 7809lp is provided in the table below. t able 15. ads7809 and 7809lp p in d ifferences p in n umber ads7809 7809lprp p in d ifference d escription 1-10 various various equivalent function to ads7809 pi ns 1-10 respectively. timing specifications change slightly (0 - 10 ns) for the 7809lprp due to the latchup protection circuitry on ads7809 die inputs. 15-22 various various equivalent function to ads7809 pi ns 11-18 respectively. timing specifications change slightly (0 - 10 ns) for the 7809lprp due to the latchup protection circuitry on ads7809 die inputs. 11 -- lpbit a built in test function of latchup prot ection. a ttl high level pulse for > 5 microsec- onds duration on this input will trigger la tchup protection of the device. this input shall be low during normal operation. 12 -- lpstatus latchup protection status output. th is ttl level output is low during normal opera- tion and goes high during a 10 s decisi on time period prior to power being removed. if the latch up current does not last at least 10 s then lptstatus will go low (inactive) after the 10 s decisi on period without power being removed. when latchup protection is triggered, this output will go high for the duration of the time that power is removed from the pr otected device (50 s). all output except lpstatus are invalid during the time t hat power is removed from the ads7809 die. this output foes low within 1 us of the power being re-applied to the protected device. functional operation of the device is within ~25 s after the lpstatus output returns low with degraded accuracy due to the latchup filter circuitry. full accuracy is restored ~5 ms later. this output can be used to inform the system pro- cessor of the latchup protection tri gger and the subsequent degraded accuracy in the 7809lprp output data. output pull-up resistors should be 10k ? or larger on outputs. i/o pins must not be driven high while this signal is active. 13 vana vana equivalent function to ads7809 pin 19. analog supply input. 14 vdig vdig equivalent function to ads7809 pin 20. digital supply input. 23 -- lpvana latchup protected analog supply pi n to the ads7809 die. decouple to analog ground with 0.1 f ceramic capacitor. do not exceed 0.2 f. do not connect to vdig and/or vana. 24 -- lpvdig latchup protected digital supply pin to the ads7809 die. decouple to digital ground with 0.1 f ceramic capacitor. do not exceed 0.2 f. do not connect to vdig and/ or vana.
memory 17 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 testing the 7809lprp latc hup protection circuitry the lpvana and lpvdig pins provide direct access to th e 7809lp converter supply pins for attaching external decoupling capacitors to ground. these pins can also be used to test the lpt tm operation and threshold level by sink- ing a pulsed current load to ground as shown in the test circuit in figure 8. the most accurate threshold current mea- surements are made with the ads7809 in its lowest power state (pwrd = 5v). the lpt tm operation and device recovery times are most easily measured using the lpbit input to trigger protection and recovery. applying a 10 sec high duration ttl level to the lpbit pin causes internal test currents sufficient to trigger the lpt tm circuit to be drawn through both the analog and digital supply sense circuits. lpt tm operating characteristics are summarized in table 16 according to the timing diagram shown in figure 9. dur- ing the time that the power is cycled, ou tput signals and data from the 7809lp are invalid. the lpstatus signal high indicates that power is removed from the ads7809 die. when this signal is low, power is applied to the ads7809 die. the lpstatus signal is used to measure the supply recovery time. the supply recovery time interval starts when the supply current rises (causing lpstatus to go high) and ends when the lpstatus signal stabilizes low again. within the functional recovery time interval (~25 sec after the lpt tm circuit reapplies power), the normal functional operation of the converter is restored with less than 5% fu ll scale error. additional settling time is then required to return to full accuracy operation. recovery time intervals are defined which indi cate the time to reco ver first to within 8 bit accuracy, then to within 12 bit accu racy, and finally to full 16 bit accuracy. these recovery times are primarily due to the single event and power cycling effects on the reference circuits and the settling times of their respective filter capacitors. t able 16. 7809lp lpt tm o perating c haracteristics p arameter s ymbol c onditions t yp u nit supply threshold current ithr pwrd = 5v 50 ma protection time tpt lpbit = 2.4v for 5 s 1 sec supply recovery time tsr lpbit = 2.4v for 5 s 50 sec functional recovery time tfr lpbit = 2.4v for 5 s tsr + 25 sec 8-bit accuracy recovery time t8r lpbit = 2.4v for 5 s 80 sec full accuracy recovery time tfar lpbit = 2.4v for 5 s 5 msec
memory 18 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 8. 7809lp lpt tm t est c ircuit gnd pulse generator 2 -7.5v gnd gnd gnd gnd +5v pulse generator 1 gnd gnd 0v 20 usec pulsewidth -vp is digital control and monitoring .4v 2.4v 5 usec pulsewidth rt/ft < 10 ns q1 2n2369a d2 1n4149 d1 1n4149 r3 50 r1 200 r2 100 r3 22.9k c1 2.2uf + c2 2.2uf + u? 7809lprp r1in 1 agnd1 2 r2in 3 r3in 4 cap 5 ref 6 agnd2 7 sb/btc 8 ext/int 9 dgnd 10 lpbit 11 lpstatus 12 vana 13 vdig 14 sync 15 dataclk 16 data 17 tag 18 r/c 19 cs 20 busy 21 pwrd 22 lpvana 23 lpvdig 24 c3 10uf + s1 c4 .1uf c4 .1uf
memory 19 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 9. 7809lp lpt tm t iming d iagram supply current (is) is (typ) 0v outputs valid ithr tfar <1/4096 f.s. tsr -vp full accuracy full scale (f.s.) lpstatus charge current into 0v - full scale all outputs is peak tfr 0 is (typ) outputs t12r >-1/20 f.s. pulse generator 2 <1/256 f.s. output data error t8r full accuracy <1/20 f.s. decoupling capacitor tpt 5v pulse generator 1 .4v 2.4v lpbit invalid outputs valid
memory 20 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f igure 10. sel c ross s ection f igure 11. seu c ross s ection
memory 21 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 f24-01 note: all dimensions in inches 24-p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.157 0.170 0.183 b 0.015 0.017 0.022 c 0.004 0.005 0.009 d -- 0.596 0.640 e 0.350 0.400 0.420 e1 -- -- 0.450 e2 0.180 0.236 -- e3 0.030 0.082 -- e 0.050 bsc l 0.315 0.325 0.335 q 0.026 0.053 0.056 s1 0.005 0.015 -- n24
memory 22 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 important notice: these data sheets are created using the chip manufacturer s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
memory 23 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 16-bit latchup protected an alog to digital converter 7809lp 12.19.01 rev 3 1000585 product ordering options model number feature option details 7809lp rp f x screening flow package radiation feature base product nomenclature multi chip module (mcm) k = maxwell class k h = maxwell class h e = engineering (testing @ +25c ) i = industrial (testing @ -40c, +25c, +85c) f = flat pack rp = r ad -p ak ? package 16-bit latchup protected analog to digital converter

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